1. Field of the Invention
This invention relates generally to driving electronic displays, and more particularly to a display driver circuit and methods for driving a multi-pixel liquid crystal display. Even more particularly, the present invention relates to a driver circuit and methods for driving a liquid crystal on silicon display device with a digital backplane.
2. Description of the Background Art
FIG. 1 shows a block diagram of a prior art display driver 100 for driving an imager 102, which includes a pixel array 104 having 1280 columns and 768 rows. Display driver 100 also includes a select decoder 105, a row decoder 106, and a timing generator 108. In addition to pixel array 104, imager 102 also includes an input buffer 110, which receives and stores 4-bit video data from a system (e.g., a computer that is not shown). Timing generator 108 generates timing signals by methods well known to those skilled in the art, and provides the timing signals to select decoder 105 and row decoder 106 via a timing signal line 112 to coordinate the modulation of pixel array 104.
Video data is written into input buffer 110 according to methods well known in the art. In the present embodiment, input buffer 110 stores a single frame of video data for each pixel in pixel array 104. When input buffer 110 receives a command from the system (not shown), input buffer 110 asserts video data for each pixel of a particular row of pixel array 104 onto all 1280 output terminals 114. In the present example, input buffer 110 must be sufficiently large to accommodate four bits of video data for each pixel of pixel array 104. Therefore, input buffer 110 is approximately 3.93 Megabits (i.e., 1280×768×4 bits) in size. Of course, if the number of bits in the video data increases (e.g., 8-bit video data), then the required capacity of input buffer 110 would necessarily increase proportionately.
The size requirement of input buffer 110 is a significant disadvantage. First, the circuitry of input buffer 110 occupies space on imager 102. As the required memory capacity increases, the chip space required by input buffer 110 also increases, thus hindering the ever present objective of size reduction in integrated circuits. Further, as the memory capacity increases, the number of storage devices increases, thereby increasing the probability of manufacturing defects, which reduces the yield of the manufacturing process and increase the cost of imager 102.
There have been attempts to reduce the size of input buffer 110. However, any such reduction comes at the expense of a significant increase in the bandwidth required to write the video data into input buffer 110 and/or an increase in the size of off-chip memory. For example, if input buffer 110 has a capacity smaller than one frame of video data, then the same video data may need to be written into input buffer 110 more than once in order to write a single frame of data to pixel array 104.
Row decoder 106 receives row addresses from the system (not shown) via a row address bus 116, and responsive to a store command from timing generator 108, row decoder 106 stores the asserted row address. Then, responsive to row decoder 106 receiving a decode instruction from timing generator 108, row decoder 106 decodes the stored row address and enables one of 768 word-lines 118 corresponding to the decoded row address. Enabling word-line 118 causes data being asserted on data output terminals 114 of input buffer 110 to be latched into the enabled row of pixel cells in pixel array 104.
Select decoder 105 receives block addresses from the system (not shown) via a block address bus 120. Responsive to receiving a store block address command from timing signal generator 108 via timing signal line 112, select decoder 105 stores the asserted block address therein. Then, responsive to timing generator 108 asserting a load block address instruction on timing signal line 112, select decoder 105 decodes the asserted block address and asserts a block update signal on one of 24 block select lines 122 corresponding to the decoded block address. The block update signal on the corresponding block select line 122 causes all of the pixels cells of an associated block of rows (i.e., 32 rows) of pixel array 104 to assert the previously latched video data onto their associated pixel electrodes (not shown in FIG. 1).
FIG. 2A shows an example dual-latch pixel cell 200(r,c,b) of imager 102, where (r), (c), and (b) indicate the row, column, and block of the pixel cell, respectively. Pixel cell 200 includes a master latch 202, a slave latch 204, a pixel electrode 206 (e.g., a mirror electrode overlying the circuitry layer of imager 102), and switching transistors 208, 210, and 212. Master latch 202 is a static random access memory (SRAM) latch. One input of master latch 202 is coupled, via transistor 208, to a Bit+ data line 214(c), and the other input of master latch 202 is coupled, via transistor 210, to a Bit− data line 216(c). The gate terminals of transistors 208 and 210 are coupled to word line 118(r). The output of master latch 202 is coupled, via transistor 212, to the input of slave latch 204. The gate terminal of transistor 212 is coupled to block select line 122(b). The output of slave latch 204 is coupled to pixel electrode 206.
An enable signal on word line 118(r) places transistors 208 and 210 into a conducting state, causing the complementary data asserted on data lines 214(c) and 216(c) to be latched, such that the output of master latch 202 is at the same logic level as data line 214(c). A block select signal on block select line 122(b) places transistor 212 into a conducting state, and causes the data being asserted on the output of master latch 202 to be latched onto the output of slave latch 204, and thus onto pixel electrode 206.
Although the master-slave latch design functions well, it is a disadvantage that each pixel cell requires two storage latches. It is also a disadvantage that separate circuitry is required to write data to the pixel cells and to cause the stored data to be asserted on the pixel electrode.
FIG. 2B shows the light modulating portion of pixel cell 200 (r, c, b) in greater detail. Pixel cell 200 further includes a portion of a liquid crystal layer 218, contained between a transparent common electrode 220 and pixel storage electrode 206. Liquid crystal layer 218 rotates the polarization of light passing through it, the degree of rotation depending on the root-mean-square (RMS) voltage across liquid crystal layer 218.
The ability to rotate the polarization is exploited to modulate the intensity of reflected light as follows. An incident light beam 222 is polarized by a polarizer 224. The polarized beam then passes through liquid crystal layer 218, is reflected off of pixel electrode 206, and passes again through liquid crystal layer 218. During this double pass through liquid crystal layer 218, the beam's polarization is rotated by an amount which depends on the data being asserted on pixel electrode 206 by slave latch 204 (FIG. 2A). The beam then passes through polarizer 226, which passes only that portion of the beam having a specified polarity. Thus, the intensity of the reflected beam passing through polarizer 226 depends on the amount of polarization rotation induced by liquid crystal layer 218, which in turn depends on the data being asserted on pixel electrode 206 by slave latch 204.
A common way to drive pixel electrode 206 is via pulse-width-modulation (PWM). In PWM, different gray scale levels (i.e., intensity values) are represented by multi-bit words (i.e., binary numbers). The multi-bit words are converted to a series of pulses, whose time-averaged root-mean-square (RMS) voltage corresponds to the analog voltage necessary to attain the desired gray scale value.
For example, in a 4-bit PWM scheme, the frame time (time in which a gray scale value is written to every pixel) is divided into 15 time intervals. During each interval, a signal (high, e.g., 5V or low, e.g., 0V) is asserted on the pixel storage electrode 106. There are, therefore, 16 (0-15) different gray scale values possible. The actual value displayed depends on the number of “high” pulses asserted during the frame time. The assertion of 0 high pulses corresponds to a gray scale value of 0 (RMS 0V), whereas the assertion of 15 high pulses corresponds to a gray scale value of 15 (RMS 5V). Intermediate numbers of high pulses correspond to intermediate gray scale levels.
FIG. 3 shows a series of pulses corresponding to the 4-bit gray scale value (1010), where the most significant bit is the far left bit. In this example of binary-weighted pulse-width modulation, the pulses are grouped to correspond to the bits of the binary gray scale value. Specifically, the first group B3 includes 8 intervals (23), and corresponds to the most significant bit of the value (1010). Similarly, group B2 includes 4 intervals (22) corresponding to the next most significant bit, group B1 includes 2 intervals (21) corresponding to the next most significant bit, and group B0 includes 1 interval (20) corresponding to the least significant bit. This grouping reduces the number of pulses required from 15 to 4, one for each bit of the binary gray scale value, with the width of each pulse corresponding to the significance of its associated bit. Thus, for the value (1010), the first pulse B3 (8 intervals wide) is high, the second pulse B2 (4 intervals wide) is low, the third pulse B1 (2 intervals wide) is high, and the last pulse B0 (1 interval wide) is low. This series of pulses results in an RMS voltage that is approximately
      2    3  (10 of 15 intervals) of the full value (5V), or approximately 4.1V.
Because the liquid crystal cells are susceptible to deterioration due to ionic migration resulting from a DC voltage being applied across them, the above described PWM scheme is modified as shown in FIG. 4. The frame time is divided in half. During the first half, the PWM data is asserted on the pixel storage electrode, while the common electrode is held low. During the second half of the frame time, the complement of the PWM data is asserted on the pixel storage electrode, while the common electrode is held high. This results in a net DC component of 0V, avoiding deterioration of the liquid crystal cell, without changing the RMS voltage across the cell, as is well known to those skilled in the art. Although pixel array 104 is debiased, the bandwidth between input buffer 110 and pixel array 104 is increased to accommodate the increased number of pulse transitions.
The resolution of the gray scale can be improved by adding additional bits to the binary gray scale value. For example, if 8 bits are used, the frame time is divided into 255 intervals, providing 256 possible gray scale values. In general, for (n) bits, the frame time is divided into (2n−1) intervals, yielding (2n) possible gray scale values.
If the PWM data shown in FIG. 4 was written to pixel cell 200 of pixel array 104 then the digital value of pixel electrode 206 would transition between a digital high and digital low value six times within the frame. It is well known that there is a delay between when the data is first asserted on pixel electrode 206 and when the intensity output of pixel 200 actually corresponds to the steady state RMS voltage of the grayscale value being asserted. This delay is referred to as the “rise time” of the cell, and results from the physical properties of the liquid crystals. The cell rise time can cause undesirable visual artifacts in the image produced by pixel array 104 such as blurred moving objects and/or moving objects that leave ghost trails. In any case, the severity of the aberrations in the visual image increases with an increase of pulse transitions asserted on pixel electrode 206. Further, visually perceptible aberrations result from the assertion of opposite digital values on adjacent pixel electrodes for a significant portion of the frame time, at least in part to the lateral field affect between adjacent pixels.
What is needed, therefore, is a system and method for driving a display that reduces the number of pulse transitions experienced by the pixels of a display. What is also needed is a system and method that reduces the amount of input memory and bandwidth needed to drive the display. What is also needed is a system and method that reduces visually perceptible aberrations in images generated by a display. What is also needed is a driving circuit and method that can drive pixel arrays with only one storage latch per pixel.